Semiconductor amplifiers are widely used for amplification of analog signals. In particular, a semiconductor differential amplifier is basically configured by a differential pair 102 including a current source 101 as shown in FIG. 1.
Due to development of the CMOS (Complementary Metal Oxide-Semiconductor) integrated circuit technology, both digital circuits and analog circuits become to be integrated on the same substrate as used for the CMOS integrated circuit. Integration of various types of circuits on a single substrate enables miniaturization of the system and reduction in cost of the products.
Such a development in integrated circuits has been achieved by size reduction of devices. The size reduction of devices leads to improvement of the circuit performance, especially of the digital circuit which is a main part of the integrated circuit. In other words, an operation speed is improved, power consumption is reduced, and a device area is decreased. A benefit to the analog circuits due to the size reduction of devices is an increase in the cut off frequency.
However, constraints on the design of an analog circuit also increase at the same time. One of them is a reduction in the input common-mode range (CMR), resulting from the scaling of a power supply voltage. That is, when reduction in a power supply voltage, required according to reduction in device dimension, is performed, an input range is significantly reduced unless reducing the threshold voltage. In addition, on the output node, stacked transistors can not be operated in the saturation region due to scaling down of the power supply voltage. In FIG. 1, this problem becomes significant when the current source 101 is implemented by a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
This contradiction in the design appears especially in a low power system. That is, for the integrated circuit with low power consumption, the threshold voltage is designed to be high in order to prevent a leakage current in the digital circuit part. For integrating an analog circuit part together with such an integrated circuit, some remedies are needed.
One of the solutions to this problem is to introduce transistors with a high breakdown voltage prepared for input and output circuits in addition to the digital circuit core. However, since it is difficult to shorten the gate length of transistors with high breakdown voltage due to its thick gate oxide film, the cutoff frequency of the transistors decreases.
A method to reduce the threshold voltage only in the analog part can also be considered, but this method requires more process steps. This problem becomes especially serious in a fin type FET which is expected to be useful when the bulk planar MOSFET becomes difficult to be scaled down. In other words, in order to change the threshold voltage in the fin type FET, changing a work function of the gate is required, thus considerable increase in the process cost for changing the work function on the same substrate is expected.
In addition, even if the problem concerning with the threshold voltage is solved, another problem concerning with the reduction in signal amplitude on the output remains unsolved. In order to solve this problem, some new ideas must be introduced into the circuit configuration.
As a method to solve this problem, Non-Patent Document 1 proposes a method for utilizing a body bias in the bulk planar MOSFET, i.e., a method for reducing the threshold voltage by utilizing the body bias effect.
Non-Patent Document 1 discloses following two methods.
The first method is to effectively reduce the threshold voltage by applying a forward bias Vref0 to the bulk terminal of the differential pair of the input transistors in the differential amplifier as shown in FIG. 2. Furthermore, to keep output voltage amplitude, no stacked transistor is used. However, since a large forward bias can not be applied as a body bias in a bulk planar MOSFET, an input voltage range is limited.
The second method disclosed in Non-Patent Document 1 is to detect the common-mode output signal as shown in FIG. 3, and to apply this common-mode component to the gates of the differential pair of the input transistors similarly to a body bias. Also in this method, a range of the feedback voltage is limited.
Non-Patent Document 1: IEEE Journal of Solid-State Circuits, Vol. 40, No. 12, pp. 2373-2387, December 2005.